This invention relates to an integrated comparator circuit widely used for pin electronics in automatic test equipment (ATE).
In a semiconductor test system, pin electronics provide an interface to the device under test (DUT). The pin electronics interface is generally realized with an application specific integrated circuit (ASIC) in order to reduce the size of the pin electronics. Size reduction is necessary for achieving a high pin-count test system (such as over 1000 pins). The ASIC pin electronics also eliminate multiple reflections by eliminating the circuit board stubs that are inevitably present in discrete implementations. Signal integrity improvement and size reduction realized by ASIC implementation are essential for high-speed (over 1 GHz) test systems.
Recently, there has been an increased demand for accurate testing of high-speed differential signals. Many state-of-the-art high-speed devices now realize higher data rates by using differential signaling to improve signal integrity and timing accuracy. However, conventional pin electronics are designed for testing single-ended signals, not for testing differential signals.
FIG. 1 illustrates one configuration used to test DUT pins 34a and 34b using two conventional single-ended pin electronics 36 and 38. Pin electronics interface 36 generally consists of driver 36a and a window comparator consisting of high comparator circuit 36b and low comparator circuit 36c. Similarly, pin electronics interface 38 includes driver 38a and a window comparator consisting of high comparator circuit 38b and low comparator circuit 38c. Thus, conventional pin electronics interface 36 is single-ended for DUT pin 34a, while pin electronics interface 38 is single-ended for DUT pin 34b. Using pin electronics interface 36 as an example, the driver circuit 36a sends formatted signals to DUT pin 34a. High comparator circuit 36b and low comparator circuit 36c receive signals from DUT pin 34a and compare the received signals with reference voltages. The input stages of high comparator circuit 36b and low comparator circuit 36c are realized by an identical circuit. Only the output logic from high comparator circuit 36b and low comparator circuit 36c is different.
FIG. 2 shows a conventional single-ended comparator circuit 10, such as high comparator circuit 36b or low comparator circuit 36c of FIG. 1. Conventional comparator circuit 10 compares the DUT signal that is applied to the base 12 of transistor 14 with a reference voltage applied to the base 16of second transistor 18. Comparator circuit 10 consists of emitter follower stages (transistor 14/transistor 18), switch stages (transistor 20/transistor 22), cascode stages (transistor 24/transistor 26) and an additional gain stage 28. The emitter follower stages (transistor 14/transistor 18) eliminate the level error caused by the base current of the switch stages (transistor 20/transistor 22). The cascode stages (transistor 24/transistor 26) reduce crosstalk from DUT signal 12 to the input of additional gain stage 28. Schottky diodes 30, 31, 32, and 33 protect the switch stage (transistor 20/transistor 22) against reverse breakdown.
Unfortunately, when using conventional comparator circuit 10 of FIG. 2 in the pin electronics configuration shown in FIG. 1, not all test modes required for differential signaling can be provided. Only P-channel comparison and N-channel comparison can be realized with conventional comparator circuit 10. Conventional comparator circuit 10 cannot realize differential comparison mode or common-mode comparison mode.
FIGS. 3A, 3B, 3C(i), 3C(ii), and 3(D) summarize the comparator test modes required for differential signaling. FIG. 3A is the P-channel comparison mode, where the P-channel of the DUT input (DUT_P) is compared with a high P-channel reference voltage (VOH_P) and a low P-channel reference voltage (VOL_P). As shown in FIG. 3A, the DUT_P input will fail if it is higher than the VOL_P or lower than the VOH_P, but will pass if it is lower than the VOL_P or higher than the VOH_P.
FIG. 3B is the N-channel comparison mode, where the N-channel of the DUT input (DUT_N) is compared with a high N-channel reference voltage (VOH_N) and a low N-channel reference voltage (VOL_N). The DUT_N input will pass if it is higher than VOH_N or lower than VOL_N, but will fail if lower than VOH_N or higher than VOL_N.
FIG. 3C(i) is the differential swing comparison mode, where the swing of the DUT signal (DUT_Pxe2x88x92DUT_N), as shown in FIG. 3C(ii), is compared with a high differential reference voltage (VOH_D) and a low differential reference voltage (VOL_D). The swing of the DUT signal (DUT_Pxe2x88x92DUT_N) will fail if it is higher than VOL_D or lower than VOH_D, but will pass if it is lower than VOL_D or higher than VOH_D.
FIG. 3D is the common-mode voltage comparison mode, where the common-mode voltage of the DUT swing (DUT_P+DUT_N)/2 is compared with a high common-mode reference voltage (VOH_C) and a low common-mode reference voltage (VOL_C). The common-mode voltage of the DUT signal (DUT_P+DUT_N)/2 will fail if it is higher than VOL_C or lower than VOH_C, but will pass if it is lower than VOL_C or higher than VOH_C.
Again, using conventional comparator circuit 10 of FIG. 2 in the pin electronics configuration of FIG. 1 will only realize the P-channel and the N-channel comparison modes. Conventional comparator circuit 10 cannot realize the differential swing comparison mode or the common-mode comparison mode.
FIG. 4 shows a conventional configuration used to realize the differential swing comparison mode (FIG. 3C(i) and 3C(ii)) that could not be realized by comparator circuit 10 of FIG. 2. In differential comparator circuit 40, a differential comparator stage 41 is added prior to conventional comparator circuit 10xe2x80x2. Differential comparator stage 41 has DUT_P 12a and DUT_N 12b applied through an emitter follower stage (transistor 42/transistor 44), a differential gain stage (transistor 46/transistor 48), and a cascode stage (transistor 50/transistor 52). The output of differential comparator stage 41 is coupled to a conventional comparator circuit 10xe2x80x2. The differential swing between the collectors of transistor 50 and transistor 52 is approximately given by:                                                         (              R1              )                                      (              R2              )                                ·                      (                          DUT_P              -              DUT_N                        )                          ,                            eq        .                  xe2x80x83                ⁢        1            
where R1 is resistor 53 and R2 is resistor 54. The voltage at the collector of transistor 52 is buffered by transistor 14, with optional level shift circuit 56 available if necessary to avoid saturation of transistor 20. Then, the buffered and shifted output voltage from transistor 52 is compared with a reference voltage 16 that is applied to the base of transistor 18.
One of the disadvantages of comparator circuit 40, however, is that as the input swing becomes larger, the differential gain stage (transistor 46/transistor 48) becomes nonlinear because of the change in the transconductance of transistor 46 and transistor 48. The non-linearity in turn degrades the DC accuracy of the test system. In addition, level shift circuit 56 adds offset level drift, degrades the waveform, and limits the maximum speed at which differential comparator circuit 40 can operate. Moreover, common-mode voltage comparison, as shown in FIG. 3D, cannot be realized by the differential comparator circuit 40 of FIG. 4. Consequently, conventional differential comparator circuit 40 of FIG. 4 is inadequate for accurate testing of a DUT with high-speed differential signals.
An embodiment of the present invention provides a comparator circuit that enables P-channel comparison, N-channel comparison, differential swing comparison, and common-mode voltage comparison required for testing differential signals as shown in FIGS. 3A-3D. The differential swing comparison compares the swing of the differential input (DUT_Pxe2x88x92DUT_N) with reference voltages. The common-mode voltage comparison compares the common-mode voltage of the input (DUT_P+DUT_N)/2 with reference voltages. According to another embodiment of the present invention, the comparator circuit has a control input to select one of the P-channel, N-channel, differential, or common-mode voltage comparison modes.
By using two identical transconductance amplifiers, the non-linearity of the transconductance stage is advantageously canceled out. Furthermore, by summing the currents of the transconductance amplifiers directly instead of first converting them to voltages, high-speed comparator operation can be achieved. Thus, by diverting currents from the transconductance amplifiers in various ways, eight different comparison modes can be realized according to one embodiment of the present invention.
A comparator circuit in accordance with one embodiment of the present invention includes at least one stage that has a first input terminal that receives a first test voltage, a second input terminal that receives a first reference voltage, a third input terminal that receives a second test voltage, and a fourth input terminal that receives a second reference voltage. In one embodiment, the at least one stage is a transconductance stage. In another embodiment, there are two separate transconductance stages, where the first and second input terminals are on one transconductance stage and the third and fourth input terminals are on the other transconductance stage. The at least one stage converts the voltages to signals and produces a first test signal on a first output terminal, a first reference signal on a second output terminal, a second test signal on a third output terminal, and a second reference signal on a fourth output terminal. The signals may be currents or voltages. The comparator circuit includes a switching circuit that is coupled to the output terminals of the at least one stage. The switching circuit has two output terminals. The switching circuit switchably couples its first output terminal to the first output terminal and one of the third output terminal and the fourth output terminal of the at least one transconductance stage. The switching circuit also switchably couples its second output terminal with the first output terminal and one of said third output terminal and said fourth output terminal of said at least one stage. In addition, a comparator circuit is included that is coupled to the output terminals of the switching circuit. In one embodiment, the switching circuit also includes transistors that couple selected output terminals of the at least one transconductance stage to a voltage source to realize a single-ended signals.
In another embodiment of the present invention, a method of testing a circuit includes providing a first test voltage from a first channel and a second test voltage from a second channel from said circuit. A first reference voltage and a second reference voltage are also provided. The test voltages and the reference voltages are converted to test signals and reference signals, that may be either voltages or currents. The method includes switchably combining said first test signal with one of said second reference signal and said second test signal to form a first combined signal and switchably combining said first reference signal with one of said second test signal and said second reference signal to form a second combined signal. The first combined signal and the second combined signal are then compared. By selecting the appropriate combinations, the method realizes a differential swing comparison mode and a common-mode comparison mode. Also, by disabling the appropriate test current and reference current, a single-ended comparison mode, e.g., for the P-channel or the N-channel, may be realized.